MC908GP32CPE Freescale Semiconductor, MC908GP32CPE Datasheet - Page 147

• Manufacturer Part Number: MC908GP32CPE
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP32CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.8.2 SCI Control Register 2
SCI control register 2:
SCTIE — SCI Transmit Interrupt Enable Bit
TCIE — Transmission Complete Interrupt Enable Bit
SCRIE — SCI Receive Interrupt Enable Bit
Freescale Semiconductor
•
•
•
•
•
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset
clears the SCTIE bit.
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears
the SCRIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
Enables the following CPU interrupt requests:
–
–
–
–
Enables the transmitter
Enables the receiver
Enables SCI wakeup
Transmits SCI break characters
M
0
1
0
0
1
1
Enables the SCTE bit to generate transmitter CPU interrupt requests
Enables the TC bit to generate transmitter CPU interrupt requests
Enables the SCRF bit to generate receiver CPU interrupt requests
Enables the IDLE bit to generate receiver CPU interrupt requests
Control Bits
Address:
PEN and PTY
Reset:
Read:
Write:
0X
0X
10
11
10
11
SCTIE
$0014
Bit 7
0
Figure 13-10. SCI Control Register 2 (SCC2)
Table 13-5. Character Format Selection
Start Bits
TCIE
6
0
1
1
1
1
1
1
MC68HC908GP32 Data Sheet, Rev. 10
SCRIE
5
0
Data Bits
8
9
7
7
8
8
ILIE
4
0
Character Format
Parity
None
None
Even
Even
Odd
Odd
TE
3
0
Stop Bits
1
1
1
1
1
1
RE
2
0
RWU
Character Length
1
0
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
Bit 0
SBK
0
I/O Registers
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