EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 130

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

5
5-4
System Controller
EP93xx User’s Guide
5.1.4 Software System Configuration Options
5.1.5 Clock Control
5.1.5.1 Oscillators and Programmable PLLs
There are several system configuration options selectable by the DeviceCfg and SysCfg
registers. These registers provide the selection of several pin multiplexing options and also
provide software access to the system reset configuration options. Please refer to the
descriptions of the registers,
detailed explanation.
The EP93xx uses a flexible system to generate required clocks. The clock system generates
up to 20 independent clock frequencies, some with very tight accuracy requirements, all from
a single external low-frequency crystal or other external clock source. The ARM Core is
designed so that once it has been configured, its CPU speed, bus speeds, and video clocks
may be set to a number of different speeds without affecting the speeds of other clocks in the
processor.
The EP93xx has an interface to two external crystal oscillators: 32.768 KHz and
14.7456 MHz. To generate the required high-frequency clocks, the processor uses two
phase-locked-loops (PLLs) to multiply the incoming 14.7456 MHz low frequency signal to
much higher frequencies that are then divided down by programmable dividers to produce
needed clocks. The PLLs operate independently of one another.
Figure 5-1
wherever the phrase “PLL1” is used in the figure, it applies to PLL2 as well.
Note: ASYNC boot mode is the preferred boot mode type for new designs.
14.7456
MHz
shows the PLL1 structure used in the EP93xx. Since PLL2 is identical to PLL1,
Feedback Divider
PLL1_X1FBD
PLL1_X1
Figure 5-1. Phase Locked Loop (PLL) Structure
“DeviceCfg” on page 5-25
Copyright 2007 Cirrus Logic
PLL1_X2IPD
Input Divider
Feedback Divider
PLL1_X2FBD
and
PLL1_X2
“SysCfg” on page
2^(PLL1_PS)
5-34, for a
DS785UM1
Fout