EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 218

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

7
7-36
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7.5 Registers
0x8003_000C
0x8003_022C
0x8003_001C
0x8003_002C
0x8003_003C
0x8003_004C
0x8003_005C
0x8003_0000
0x8003_0004
0x8003_0008
0x8003_0228
0x8003_0010
0x8003_0014
0x8003_0018
0x8003_0020
0x8003_0024
0x8003_0028
0x8003_0030
0x8003_0034
0x8003_0038
0x8003_0040
0x8003_0044
0x8003_0048
0x8003_0050
0x8003_0054
0x8003_0058
Address
VActiveStrtStop
HActiveStrtStop
VBlankStrtStop
HBlankStrtStop
VidScrnHPage
VSyncStrtStop
HSyncStrtStop
VidScrnPage
BkgrndOffset
VClkStrtStop
HClkStrtStop
VideoAttribs
VLinesTotal
PattrnMask
LineLength
BlinkPattrn
Brightness
VLineStep
BlinkMask
PixelMode
ScrnLines
HClkTotal
LineCarry
BlinkRate
ParllIfOut
ParllIfIn
Name
Table 7-12. Raster Engine Register List
Copyright 2007 Cirrus Logic
locked
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
SW
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Type
8 + 8 bits
11 bits
22 bits
22 bits
22 bits
22 bits
11 bits
22 bits
22 bits
22 bits
22 bits
16 bits
16 bits
32 bits
32 bits
11 bits
12 bits
13 bits
11 bits
24 bits
24 bits
24 bits
24 bits
15 bits
8 bits
9 bits
Size
Total Number of horizontal line clocks
Number of active lines scanned to the
Parallel interface read/setup register.
Starting address of video screen half
Pixel mode definition setup register.
Total Number of vertical frame lines
Horizontal/vertical offset parameter
Video state machine parameters
Starting address of video screen
Length in words of data for lines
Background color or blink offset
Compare value for determining
Logic mask applied to pixel to
Parallel interface write/control
Horizontal clock active frame
Horizontal sync pulse setup
Vertical clock active frame
Memory step for each line
Horizontal blanking setup
Vertical sync pulse setup
PWM brightness control
perform blink operation
Vertical blanking setup
Horizontal active setup
Mask to limit pattern.
Vertical active setup
Blink counter setup
blinking pixels.
Description
register.
screen
value.
page
DS785UM1