EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 436
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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10
SAR_BASEx
10-42
DMA Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
SAR_BASE0: Channel Base Address + 0x0018 - Read/Write
SAR_BASE1: Channel Base Address + 0x001C - Read/Write
This register contains the base memory address from which the DMA
controller requests data.
SAR_BASEx:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
For a double/multiple buffer transfer, the second buffer
descriptor can be programmed while the transfer using the
first buffer is being carried out (thus reducing software
latency impact). The NFB interrupt is generated when
transfer begins using the second buffer. The NFB interrupt
service routine can then be used to update the free buffer
descriptor (in the case where a third buffer is required).
If BCRx = 0 when the transfer is triggered, then NO
transfers will occur, that is, the DMA will stay in the STALL
state.
x = “0” or “1” representing the double buffer per channel.
This register contains the base memory address from
which the DMA controller requests data. At least 1 of the
SAR_BASEx registers must be programmed before the
ENABLE bit and the START bit (in the case of software-
trigger M2M mode) are set in the Control register, and also
before the corresponding BCRx register is programmed.
The second buffer descriptor can be programmed while
the transfer using the “other” buffer is being carried out
(thus reducing software latency impact). When transferring
from external device to memory, the SAR_BASEx will
contain the base address of the memory mapped device.
SAR_BASEx
SAR_BASEx
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0
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