EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 566

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

15
UART2RXSts
15-8
UART2
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808D_0004 - Read/Write
0x0000_0000
UART Receive Status Register and Error Clear Register. Provides receive
status of the data value last read from the UART2Data. A write to this register
clears the framing, parity, break and overrun errors. The data value is not
important.
RSVD:
OE:
BE:
PE:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Overrun Error. This bit is set to “1” if data is received and
the FIFO is already full. This bit is cleared to 0 by a write to
UART2RXSts. The FIFO contents remain valid since no
further data is written when the FIFO is full, only the
contents of the shift register are overwritten. The CPU
must now read the data in order to empty the FIFO.
Break Error. This bit is set to “1” if a break condition was
detected, indicating that the received data input was held
LOW for longer than a full-word transmission time (defined
as start, data, parity and stop bits). This bit is cleared to 0
after a write to UART2RXSts. In FIFO mode, this error is
associated with the character at the top of the FIFO. When
a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive
data input goes to a “1” (marking state) and the next valid
start bit is received.
Parity Error. When this bit is set to “1”, it indicates that the
parity of the received data character does not match the
parity selected in UART2LinCtrlHigh (bit 2). This bit is
cleared to 0 by a write to UART2RXSts. In FIFO mode,
this error is associated with the character at the top of the
FIFO.
24
8
RSVD
23
7
22
6
21
5
20
4
OE
19
3
BE
18
2
PE
17
1
DS785UM1
FE
16
0