EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 702

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

22
AC97ISRx
22-14
AC’97 Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
RTIS:
TCIS:
AC97ISR1 - 0x8088_0014 - Read Only
AC97ISR2 - 0x8088_0034 - Read Only
AC97ISR3 - 0x8088_0054 - Read Only
AC97ISR4 - 0x8088_0074 - Read Only
Interrupt Status Register. The AC97ISR registers are the Interrupt status
registers for the controller FIFOs. All bits are cleared to zero on reset except
for the TCIS as the FIFO and shift register should both be empty.
RSVD:
RIS:
TIS:
RTIS:
TCIS:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
RX Timeout Interrupt Status - If this bit is set to “1”, the
timeout FIFO interrupt is asserted.
TX complete Interrupt Status - If this bit is set to “1”, the
transmit FIFO complete interrupt is asserted.
Reserved. Unknown During Read.
RX Interrupt Status - If this bit is set to “1”, the receive
FIFO interrupt is asserted.
TX Interrupt Status - If this bit is set to “1”, the transmit
FIFO interrupt is asserted.
RX Timeout Interrupt Status - If this bit is set to “1”, the
timeout FIFO interrupt is asserted.
TX complete Interrupt Status - If this bit is set to “1”, the
transmit FIFO complete interrupt is asserted.
24
8
RSVD
23
7
22
6
21
5
20
4
RIS
19
3
TIS
18
2
RTIS
17
1
DS785UM1
TCIS
16
0