EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 692

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

22
22-4
AC’97 Controller
EP93xx User’s Guide
22.2.1.3 RTIS
22.2.1.4 TCIS
22.2.2 Global Interrupts
22.2.2.1 CODECREADY
22.2.2.2 WINT
22.2.2.3 GPIOINT
The receive timeout interrupt is asserted when the receive FIFO is not empty and no further
data is received over a number of frames. This number is set by the TOC value in the
AC97RXCR register. The receive timeout interrupt is cleared when the FIFO becomes empty
through reading all the data.
The transmit complete interrupt is asserted when the transmit FIFO is empty and the parallel
to serial shifter is empty. This indicates that there is no data left in the FIFOs to be sent.
The individual interrupts that are global for the AC97 controller are described below. The
status of these interrupts can be read from the AC97GIS or AC97RGIS registers, and are
masked in the AC97IM register.
The Codec Ready Interrupt is asserted when the codec has indicated that it is ready by
setting bit15 of Slot0.
This interrupt is cleared by writing a “1” to the appropriate bit of the AC97EOI register.
The Wake-up interrupt is asserted when a wake-up event will trigger the assertion of
SDATAIN while the AC-Link is powered down. The wake-up is caused by the external
codec’s GPIO pins, which have been configured to generate a wake-up event via the codec’s
GPIO pin Wake-up Control register (0x52). An AC-Link wake-up interrupt is defined as a 0-to-
1 transition on SDATAIN when the AC-Link is powered down. The controller knows when the
external codec has been powered down as the SLOT1/2TX registers are monitored to check
for this condition. When the wake up event has been detected on the SDATAIN line, an
interrupt is generated to allow the ARM Core to reactivate the link with either a warm or cold
reset.
This interrupt is cleared by writing a “1” to the appropriate bit of the AC97EOI register.
The receive GPIOINT interrupt is asserted when bit 0 in slot 12 of the incoming SDATAIN is
“1”. This bit indicates that one or more of the bits in slot 12 have changed since the last
frame. It is up to the interrupt service routine to read the AC97S12Data register in order to
clear this interrupt. The external codec’s register (0x54) GPIO pin Status reflects the state of
all of the GPIO pins.
Copyright 2007 Cirrus Logic
DS785UM1