EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 238

IC ARM920T MCU 200MHZ 352-PBGA

EP9312-IBZ

Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9312-IBZ

Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1260

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
Part Number:
EP9312-IBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
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7
ACRate
FIFOLevel
7-56
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
31
15
Address: 0x8003_0214
Default: 0x0000_0000
Definition: AC Toggle Rate register
Bit Descriptions:
Address: 0x8003_0234
Default: 0x0000_0010
Definition: FIFO Refill Level register
Bit Descriptions:
30
14
30
14
RSVD
29
13
29
13
28
12
28
12
RSVD:
RATE:
RSVD:
LEVEL:
27
27
11
11
RSVD
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved - Unknown during read
Rate - Read/Write
The RATE field must be written with a value that is one
less than the number of horizontal video lines before the
AC LCD bias signal is to toggle. Care must be taken when
choosing this value while using the grayscale dithering
algorithms, as a DC build-up may occur if the pixel timing
for the ‘on’ state of the pixel is concurrent with the bias
frequency.
Reserved - Unknown during read
Level - Read/Write
24
24
8
8
RSVD
RSVD
23
23
7
7
22
22
6
6
RATE
21
21
5
5
20
20
4
4
19
19
3
3
LEVEL
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0

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