EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 551
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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DS785UM1
RILEN:
RFLEN:
RTOEN:
FLAG:
CRCN:
CRCApd:
IDLE:
AME:
IDLSpc:
Copyright 2007 Cirrus Logic
Receive Information Lost Interrupt Enable.
0 - RIL interrupt will not occur.
1 - RIL interrupt will occur whenever RIL bit is set.
Receive Frame Lost Interrupt Enable.
0 - RFL interrupt will not occur.
1 - RFL interrupt will occur whenever RFL bit is set.
Receiver Time Out Interrupt Enable.
0 - RTO interrupt will not occur.
1 - RTO interrupt will occur whenever RTO bit is set.
Minimum number of opening and closing flags for HDLC
TX. The minimum number of flags between packets is this
4-bit value plus one. Hence, 0000b forces at least one
opening flag and one closing flag for each packet, and
1111b forces at least 16 opening and closing flags. The
closing flags of one packet may also be the opening flags
of the next one if the transmit line does not go idle in
between. Note that HDLC RX does not count flags; only
one is necessary (or three in Manchester mode).
CRC polarity control.
0 - CRC transmitted not inverted.
1 - CRC transmitted inverted.
CRC pass through.
0 - Do not pass received CRC to CPU.
1 - Pass received CRC to CPU.
Idle mode.
0 - Idle-in Mark mode - When HDLC is idle (not
transmitting starting/stop flags or packets), hold the
transmit data pin high.
1 - Idle-in Flag mode - When HDLC is idle, transmit
continuous flags.
Address Match Enable. Activates address matching on
received frames.
00 - No address matching
01 - 4 x 1 byte matching
10 - 2 x 2 byte matching
11 - Undefined, no matching
Idle in space
0 - TX idle in mark (normal)
1 - TX idle in space
RX will receive Manchester encoded data whether it idles
in mark or space.
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
14-29
14
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