EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 154

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

5
5-28
System Controller
EP93xx User’s Guide
A1onG:
A2onG:
CPENA:
U3EN:
MonG:
TonG:
GonK:
IonU2:
D0onG:
D1onG:
Copyright 2007 Cirrus Logic
I
1 - I
EGPIO[5], SDO1 is on EGPIO[4].
0 - EGPIO[5:4] are not used.
I
1 - I
EGPIO[13], SDO2 is on EGPIO[6].
0 - EGPIO[13] and EGPIO[6] are not used.
Co-processor Enable.
1 - MaverickCrunch co-processor is enabled.
0 - C o - p r o c e s s o r is d i s a b l e d a n d w i l l n o t a c c e p t
instructions.
UART3 Enable.
1 - UART3 baud rate clock is active.
0 - UART3 clock is off.
Modem on GPIO.
1 - Modem support signals use EGPIO[0] pins.
0 - Modem support signals do not use EGPIO[0] pins
TENn on GPIO. This bit has no effect unless HC3EN and
HC1EN are 0.
1 - UART3 TENn signal drives EGPIO[3].
0 - EGPIO[3] used by GPIO.
GPIO on Key Matrix.
1 - Key Matrix pins are configured for GPIO operation,
0 - Key Matrix pins are controlled by other options.
The GonK has precedence over the Key Matrix controller.
T h e S P I 0 , w h e n m a p p e d t o K e y M a t ri x p i n s , h a s
precedence over GPIO. When the Key Matrix pins are
configured for SPI0, the pins unused by SPI0 can be used
for GPIO.
IrDA on UART2.
1 - UART2 is used as an IrDA interface,
0 - UART2 is a normal UART.
External DMA0 hardware handshake signals mapped to
EGPIO pins.
1 - Signals mapped.
0 - Signals not supported.
External DMA1 hardware handshake signals mapped to
EGPIO pins.
1 - Signals mapped.
0 - Signals not supported.
2
2
S Audio Port 1 on GPIO.
S Audio Port 2 on GPIO.
2
2
S Port 1 pins are mapped to EGPIO. SDI1 is on
S Port 2 pins are mapped to EGPIO. SDI2 is on
DS785UM1