EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 723

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

DS785UM1
Microwire format is very similar to SPI format, except that transmission is half-duplex instead
of full-duplex, using a master-slave message passing technique. Each serial transmission
begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device.
During this transmission, no incoming data is received by the SSP. After the message has
been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of
the 8-bit control message has been sent, responds with the required data. The returned data
is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of
SFRMOUT causes the value contained in the bottom entry of the transmit FIFO to be
transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control
frame to be shifted out onto the SSPTXD pin. SFRMOUT remains LOW for the duration of the
frame transmission. The SSPRXD pin remains in a high impedance state during this
transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge
of each SCLKOUT. After the last bit is latched by the slave device, the control byte is
decoded during a one clock wait-state, and the slave responds by transmitting data back to
the SSP. Each bit is driven onto SSPRXD line on the falling edge of SCLKOUT. The SSP in
turn latches each bit on the rising edge of SCLKOUT. At the end of the frame, for single
transfers, the SFRMOUT signal is pulled HIGH one clock period after the last bit has been
latched in the receive serial shifter, that causes the data to be transferred to the receive FIFO.
For continuous transfers, data transmission begins and ends in the same manner as a single
transfer. However, the SFRMOUT line is continuously asserted (held LOW) and transmission
of data occurs back to back. The control byte of the next frame follows directly after the LSB
of the received data from the current frame. Each of the received values is transferred from
the receive shifter on the falling edge SCLKOUT, after the LSB of the frame has been latched
into the SSP.
Note: The off-chip slave device can put the receive line in a high impedance state either on the
• the SCLKOUT signal is forced LOW
• SFRMOUT is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
falling edge of SCLKOUT after the LSB has been latched by the receive shifter, or when
the SFRMOUT pin goes HIGH.
Copyright 2007 Cirrus Logic
Synchronous Serial Port
EP93xx User’s Guide
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