EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 799

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

DS785UM1
28.2 Registers
When the GPIO port signals are not explicitly mapped to a device pin, the inputs will continue
to monitor the pin while outputs are disconnected. For example, when the Key Matrix block
has control of the ROW pins, GPIO port C inputs still monitor the state of the ROW pins.
Another level of functional muxing is applied to several EGPIO pins. The Syscon DeviceCfg
register bits RonG, MonG, TonG, HC3EN, HC1EN, and map different functionality to the
EGPIO pins:
Some GPIO signals are used as inputs by other functional blocks. EGPIO[2:1] are routed to
the DMA controller to allow for external DMA requests. IDE interface input signals DMARQ
and DASPn are EGPIO[2] and EGPIO[15], respectively.
Note: The various functional modes described in
• MonG maps RI (modem Ring Indicator) onto EGPIO[0].
• RonG maps CLK32K, the 32 KHz clock monitor output for RTC calibration, onto
• TonG maps TENn, the RS485 transmit enable output, onto EGPIO[3].
• Both HC3EN and HC1EN map the synchronous HDLC clock onto EGPIO[3].
10. COL[7:0] are the Key Matrix column pins.
EGPIO[1].
0x8084_000C
0x8084_001C
0x8084_002C
0x8084_003C
0x8084_004C
0x8084_0000
0x8084_0004
0x8084_0008
0x8084_0010
0x8084_0014
0x8084_0018
0x8084_0020
0x8084_0024
0x8084_0028
0x8084_0030
0x8084_0034
0x8084_0038
0x8084_0040
0x8084_0044
0x8084_0048
DeviceCfg register in Syscon. See
register information.
Address
Read Location
GPIOFIntType1
PCDDR
PDDDR
PGDDR
PHDDR
PADDR
PBDDR
PEDDR
PFDDR
PBDR
PCDR
PDDR
PEDR
RSVD
RSVD
PGDR
PHDR
RSVD
PADR
PFDR
Table 28-5. GPIO Register Address Map
Copyright 2007 Cirrus Logic
Chapter
Table 28-4
5,
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
“DeviceCfg” on page 5-25
are selected via bits set in the
Write Location
GPIOFIntType1
PCDDR
PDDDR
PGDDR
PHDDR
PADDR
PBDDR
PEDDR
PFDDR
PBDR
PCDR
PDDR
PEDR
RSVD
RSVD
PGDR
PHDR
RSVD
PADR
PFDR
for additional
EP93xx User’s Guide
Reset Value
GPIO Interface
Note 1
Note 1
Note 1
Note 1
Note 2
Note 1
Note 1
Note 1
0x0C
0x00
0x00
0x00
0x00
0x03
0x00
0x00
0x00
-
-
-
28-9
28