AT89LP214-20XU Atmel, AT89LP214-20XU Datasheet - Page 14

• Manufacturer Part Number: AT89LP214-20XU
• Description: MCU 8051 2K FLASH 20MHZ 14-TSSOP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP214-20XU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Package: 14TSSOP
• Device Core: 8051
• Family Name: AT89
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/UART
• Number Of Timers: 2
• Core: 8051
• Processor Series: AT89x
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 128 B
• Mounting Style: SMD/SMT
• Height: 1.05 mm
• Length: 5.1 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.4 V
• Width: 4.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Table 9-2.
10. Reset
10.1
14
TPS3
TPS2
TPS1
TPS0
CDV1
CDV0
COE
Symbol
CLKREG = 8FH
Not Bit Addressable
Bit
Power-on Reset
AT89LP213/214
Function
Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1 and the Watchdog Timer. The prescaler
is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with the value stored in the
TPS bits to give a division ratio between 1 and 16. By default the timers will count every clock cycles (TPS = 0000B). To
configure the timers to count at a standard 8051 rate of once every 12 clock cycles, TPS should be set to 1011B.
Clock Out Division. Determines the frequency of the clock output relative to the system clock.
CDIV1
0
0
1
1
Clock Out Enable. Set COE to output a divided version of the system clock on XTAL2 (P3.3). The internal RC oscillator
or external clock source must be selected in order to use this feature.
CLKREG
TPS3
7
– Clock Control Register
CDIV0
0
1
0
1
During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the
program starts execution from the Reset Vector, 0000H. The AT89LP213/214 has five sources
of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset.
A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level is
nominally 1.4V. The POR is activated whenever V
cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices
without a brown-out detector. The POR circuit ensures that the device is reset from power-on. A
power-on sequence is shown in
Reset threshold voltage V
ization sequence completes, the start-up timer determines how long the device is kept in POR
after V
POR threshold level. A Power-on Reset (i.e. a cold reset) will set the POF flag in PCON. The
internally generated reset can be extended beyond the power-on period by holding the RST pin
low longer than the time-out.
TPS2
6
CC
Clock Out Frequency
f/2
f/4
f/8
f/16
rise. The POR signal is activated again, without any delay, when V
TPS1
5
POR
TPS0
, an initialization sequence lasting t
4
Figure 10-1 on page
–
3
CC
is below the detection level. The POR cir-
CDV1
2
15. When V
Reset Value = 0000 0000B
POR
CDV0
is started. When the initial-
CC
1
reaches the Power-on
CC
3538E–MICRO–11/10
COE
falls below the
0