AT89LP214-20XU Atmel, AT89LP214-20XU Datasheet - Page 76

• Manufacturer Part Number: AT89LP214-20XU
• Description: MCU 8051 2K FLASH 20MHZ 14-TSSOP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP214-20XU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Package: 14TSSOP
• Device Core: 8051
• Family Name: AT89
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/UART
• Number Of Timers: 2
• Core: 8051
• Processor Series: AT89x
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 128 B
• Mounting Style: SMD/SMT
• Height: 1.05 mm
• Length: 5.1 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.4 V
• Width: 4.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

23.8.6
76
AT89LP213/214
Timing Parameters
The timing parameters for
are shown in
Table 23-6.
Note:
Symbol
t
t
t
t
t
PW RUP
t
PW RDN
t
t
t
t
t
t
t
t
t
t
SHSL
SLSH
t
t
t
CLCL
t
t
t
POR
RHZ
SCK
t
t
SOH
SOV
SOE
SOX
SSD
ERS
RLZ
SSE
ZSS
SSZ
STL
SIH
SIS
t
AW R
SR
SF
W R
1. t
SCK
Parameter
System Clock Cycle Time
Power On to SS High Time
Power-on Reset Time
SS Tristate to Power Off
RST Low to I/O Tristate
RST Low Settling Time
RST High to SS Tristate
Serial Clock Cycle Time
Clock High Time
Clock Low Time
Rise Time
Fall Time
Serial Input Setup Time
Serial Input Hold Time
Serial Output Hold Time
Serial Output Valid Time
Output Enable Time
Output Disable Time
SS Enable Lead Time
SS Disable Lag Time
SCK Setup to SS Low
SCK Hold after SS High
Write Cycle Time
Write Cycle with Auto-Erase Time
Chip Erase Cycle Time
Table
Programming Interface Timing Parameters
is independent of t
23-6.
Figure
CLCL
23-5,
.
Figure
23-6,
Figure
200
t
t
t
Min
100
CLCL
SLSH
SLSH
2.5
7.5
10
75
50
10
10
25
25
0
0
5
(1)
23-7,
Figure
2 t
2 t
Max
100
60
25
25
10
35
10
25
CLCL
CLCL
1
23-8, and
3538E–MICRO–11/10
Units
ms
ms
ms
Figure 23-10
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns