AT89LP214-20XU Atmel, AT89LP214-20XU Datasheet - Page 55

• Manufacturer Part Number: AT89LP214-20XU
• Description: MCU 8051 2K FLASH 20MHZ 14-TSSOP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP214-20XU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Package: 14TSSOP
• Device Core: 8051
• Family Name: AT89
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/UART
• Number Of Timers: 2
• Core: 8051
• Processor Series: AT89x
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 128 B
• Mounting Style: SMD/SMT
• Height: 1.05 mm
• Length: 5.1 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.4 V
• Width: 4.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 18-4. SPI Transfer Format with CPHA = 0
Note:
Figure 18-5. SPI Transfer Format with CPHA = 1
Note:
3538E–MICRO–11/10
*Not defined but normally MSB of character just received.
(FOR REFERENCE)
*Not defined but normally LSB of previously transmitted character.
(FROM MASTER)
SCK (CPOL = 0)
SCK (CPOL = 1)
SS (TO SLAVE)
(FROM SLAVE)
SCK CYCLE #
MOSI
MISO
The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate =
baud rate) bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possi-
ble clock rates when the SPI is in master mode. In slave mode, the SPI will operate at the rate of
the incoming SCK as long as it does not exceed the maximum bit rate. There are also four pos-
sible combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL
determine which format is used for transmission. The SPI data transfer formats are shown in
Figures 18-4 and
and SPR should not be modified while the interface is enabled, and the master device should be
enabled before the slave device(s).
*
MSB
MSB
1
18-5. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL,
2
6
6
3
5
5
4
4
4
5
3
3
6
2
2
7
1
1
AT89LP213/214
8
LSB
LSB
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