AT89LP214-20XU Atmel, AT89LP214-20XU Datasheet - Page 9

• Manufacturer Part Number: AT89LP214-20XU
• Description: MCU 8051 2K FLASH 20MHZ 14-TSSOP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP214-20XU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Package: 14TSSOP
• Device Core: 8051
• Family Name: AT89
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/UART
• Number Of Timers: 2
• Core: 8051
• Processor Series: AT89x
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 128 B
• Mounting Style: SMD/SMT
• Height: 1.05 mm
• Length: 5.1 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.4 V
• Width: 4.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7. Special Function Registers
Table 7-1.
Notes:
3538E–MICRO–11/10
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
0F8H
0F0H
98H
90H
88H
80H
1. All SFRs in the left-most column are bit-addressable.
2. Reset value is xx11 1111B when Tristate-Port Fuse is enabled and xx00 0000B when disabled.
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
000x x000
x000 0000
xx11 1111
SCON
TCON
SPSR
PSW
ACC
P3
P1
IP
IE
B
8
0
AT89LP213/214 SFR Map and Reset Values
0000 0000
0000 0000
0000 0000
0010 0100
0000 0000
0000 0111
xxxx xxxx
SADDR
TCONB
SADEN
TMOD
SPCR
SBUF
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect. User software should not write to these unlisted
locations, since they may be used in future products to invoke new features.
SP
9
1
7-1.
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx 0xxx
GPMOD
P1M0
AUXR1
SPDR
DPL
RL0
TL0
A
2
(2)
0000 0000
0000 0000
0000 0000
0000 0000
xx00 0000
P1M1
GPLS
DPH
RL1
TL1
B
3
0000 0000
0000 0000
0000 0000
GPIEN
RH0
TH0
C
4
0000 0000
0000 0000
0000 0000
GPIF
RH1
TH1
D
5
(write-only)
WDTRST
P3M0
E
6
AT89LP213/214
(2)
x000 0000
0000 x000
0000 x000
0000 0000
xx00 0000
xx00 0000
WDTCON
CLKREG
PCON
ACSR
P3M1
IPH
F
7
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
9