AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 109

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.9
12.9.1
7679H–CAN–08/08
8-bit Timer/Counter Register Description
Timer/Counter0 Control Register A – TCCR0A
Figure 12-10
Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f
Figure 12-11
Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written
when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-
pare match is forced on the Waveform Generation unit. The OC0A output is changed according
to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is
the value present in the COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
Bit
Read/Write
Initial Value
TCNTn
TCNTn
(clk
(clk
OCRnx
OCRnx
OCFnx
(CTC)
OCFnx
clk
clk
clk
clk
I/O
I/O
I/O
I/O
Tn
Tn
/8)
/8)
shows the setting of OCF0A in all modes except CTC mode.
shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
FOC0A
caler (f
W
7
0
clk_I/O
WGM00
R/W
6
0
/8)
OCRnx - 1
TOP - 1
COM0A1
R/W
5
0
COM0A0
R/W
4
0
WGM01
OCRnx
TOP
R/W
3
0
OCRnx Value
TOP
CS02
R/W
2
0
AT90CAN32/64/128
CS01
R/W
OCRnx + 1
BOTTOM
1
0
CS00
R/W
0
0
TCCR0A
clk_I/O
BOTTOM + 1
OCRnx + 2
/8)
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