AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 140

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.11.6
13.11.7
13.11.8
140
AT90CAN32/64/128
Timer/Counter3 Control Register C – TCCR3C
Timer/Counter1 – TCNT1H and TCNT1L
Timer/Counter3 – TCNT3H and TCNT3L
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to zero
when TCCRnA is written when operating in a PWM mode. When writing a logical one to the
FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on the Waveform Genera-
tion unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting.
Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value
present in the COMnx1:0 bits that determine the effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnC bits are always read as zero.
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers.
Registers” on page 116.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
FOC3A
R/W
R/W
R/W
7
0
7
0
7
0
FOC3B
R/W
R/W
R/W
6
0
6
0
6
0
FOC3C
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R
TCNT1[15:8]
TCNT3[15:8]
4
–
0
4
0
4
0
TCNT1[7:0]
TCNT3[7:0]
R/W
R/W
3
0
3
0
R
3
–
0
R/W
R/W
2
0
2
0
R
2
–
0
R/W
R/W
1
0
1
0
R
1
–
0
R/W
R/W
0
0
0
0
R
0
–
0
See “Accessing 16-bit
TCNT1H
TCNT1L
TCNT3H
TCNT3L
TCCR3C
7679H–CAN–08/08