AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 290

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.8.3
290
AT90CAN32/64/128
The ADC Data Register – ADCL and ADCH
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the
ADC.
Table 21-5.
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input
channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then
ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
Bit
Bit
Read/Write
Initial Value
Bit
Bit
Read/Write
Initial Value
ADLAR = 0
ADLAR = 1
ADPS2
0
0
0
0
1
1
1
1
ADC7
ADC9
ADC1
ADC Prescaler Selections
15
15
R
R
R
R
–
7
0
0
7
0
0
ADC6
ADC8
ADC0
14
14
R
R
R
R
–
6
0
0
6
0
0
ADPS1
0
0
1
1
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
ADPS0
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
0
1
0
1
0
1
0
1
ADC2
ADC4
10
10
R
R
R
R
–
2
0
0
–
2
0
0
ADC9
ADC1
ADC3
R
R
R
R
9
1
0
0
9
–
1
0
0
Division Factor
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
–
0
0
0
128
16
32
64
2
2
4
8
ADCH
ADCL
ADCH
ADCL
7679H–CAN–08/08