AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 125

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.7.2
13.7.3
13.8
7679H–CAN–08/08
Compare Match Output Unit
Compare Match Blocking by TCNTn Write
Using the Output Compare Unit
match had occurred (the COMnx1:0 bits settings define whether the OCnx pin is set, cleared or
toggled).
All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the
same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.
Since writing TCNTn in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNTn when using any of the Output Compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect wave-
form generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP
values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting.
The setup of the OCnx should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com-
pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value.
Changing the COMnx1:0 bits will take effect immediately.
The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses
the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match.
Secondly the COMnx1:0 bits control the OCnx pin output source.
schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR
and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx
state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset occur,
the OCnx Register is reset to “0”.
AT90CAN32/64/128
Figure 13-5
shows a simplified
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