AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 425

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7679H–CAN–08/08
20 Analog Comparator ............................................................................. 269
21 Analog to Digital Converter - ADC ..................................................... 273
22 JTAG Interface and On-chip Debug System ..................................... 293
23 Boundary-scan IEEE 1149.1 (JTAG) ................................................... 300
19.12 Examples of CAN Baud Rate Setting .............................................................266
20.1
20.2
20.3
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
22.9
22.10 Bibliography ....................................................................................................299
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
Overview .........................................................................................................269
Analog Comparator Register Description .......................................................269
Analog Comparator Multiplexed Input ............................................................271
Features ..........................................................................................................273
Operation ........................................................................................................274
Starting a Conversion .....................................................................................275
Prescaling and Conversion Timing .................................................................276
Changing Channel or Reference Selection ....................................................279
ADC Noise Canceler .......................................................................................280
ADC Conversion Result ..................................................................................284
ADC Register Description ...............................................................................287
Features ..........................................................................................................293
Overview .........................................................................................................293
Test Access Port – TAP ..................................................................................293
TAP Controller ................................................................................................296
Using the Boundary-scan Chain .....................................................................297
Using the On-chip Debug System ..................................................................297
On-chip Debug Specific JTAG Instructions ....................................................298
On-chip Debug Related Register in I/O Memory ............................................299
Using the JTAG Programming Capabilities ....................................................299
Features ..........................................................................................................300
System Overview ............................................................................................300
Data Registers ................................................................................................300
Boundary-scan Specific JTAG Instructions ....................................................302
Boundary-scan Related Register in I/O Memory ............................................304
Boundary-scan Chain .....................................................................................304
AT90CAN32/64/128 Boundary-scan Order ....................................................314
Boundary-scan Description Language Files ...................................................320
AT90CAN32/64/128
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