AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 85

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.7
7679H–CAN–08/08
Alternate Functions of Port F
Table 9-17.
Note:
The Port F has an alternate function as analog input for the ADC as shown in
some Port F pins are configured as outputs, it is essential that these do not switch when a con-
version is in progress. This might corrupt the result of the conversion. If the JTAG interface is
enabled, the pull-up resistors on pins PF7 (TDI), PF5 (TMS) and PF4 (TCK) will be activated
even if a reset occurs.
Table 9-18.
The alternate pin configuration is as follows:
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, input channel 7
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Port Pin
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
1. AIN0D and AIN1D is described in
Overriding Signals for Alternate Functions in PE3..PE0
Port F Pins Alternate Functions
Alternate Function
ADC7/TDI (ADC input channel 7 or JTAG Data Input)
ADC6/TDO (ADC input channel 6 or JTAG Data Output)
ADC5/TMS (ADC input channel 5 or JTAG mode Select)
ADC4/TCK (ADC input channel 4 or JTAG ClocK)
ADC3 (ADC input channel 3)
ADC2 (ADC input channel 2)
ADC1 (ADC input channel 1)
ADC0 (ADC input channel 0)
PE3/AIN1/OC3A
0
0
0
0
OC3A ENABLE
OC3A
0
AIN1D
0
0
AIN1 INPUT
(1)
PE2/AIN0/XCK0
0
0
0
0
UMSEL0
XCK0 OUTPUT
0
AIN0D
0
XCK0 INPUT
AIN0 INPUT
“Digital Input Disable Register 1 – DIDR1” on page
(1)
.
PE1/PDO/TXD0
TXEN0
0
TXEN0
1
TXEN0
TXD0
0
0
0
–
–
AT90CAN32/64/128
PE0/PDI/RXD0
RXEN0
PORTE0 • PUD
RXEN0
0
0
0
0
0
0
RXD0
–
Table
272.
9-18. If
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