AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 571
AT91SAM9R64-CU-999
Manufacturer Part Number
AT91SAM9R64-CU-999
Description
IC MCU ARM9 64K SRAM 144LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9R64-CU.pdf
(903 pages)
Specifications of AT91SAM9R64-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
SPI, TWI, UART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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37.3
37.3.1
Figure 37-2. DMAC Transfer Hierarchy for Memory
6289C–ATARM–28-May-09
Functional Description
Basic Definitions
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then
stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form
a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previ-
ously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMAC transfer and does not require
a handshaking interface to interact with the DMAC.
Channel: Read/write datapath between a source peripheral on one configured AMBA layer and
a destination peripheral on the same or different AMBA layer that occurs through the channel
FIFO.
Master interface: DMAC is a master on the AHB bus reading data from the source and writing it
to the destination over the AHB bus.
Slave interface: The APB interface over which the DMAC is programmed. The slave interface
in practice could be on the same layer as any of the master interfaces or on a separate layer.
Buffer: A buffer of DMAC data. The amount of data (length) is determined by the flow controller.
For transfers between the DMAC and memory, a buffer is broken directly into a sequence of
AMBA bursts and AMBA single transfers.
DMAC transfer: Software controls the number of buffers in a DMAC transfer. Once the DMAC
transfer has completed, then hardware within the DMAC disables the channel and can generate
an interrupt to signal the completion of the DMAC transfer. You can then re-program the channel
for a new DMAC transfer.
Single-buffer DMAC transfer: Consists of a single buffer.
Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buf-
fer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of
channel registers, and contiguous buffers. The source and destination can independently select
which method to use.
Transfer
AMBA
Burst
Buffer
Transfer
AMBA
Burst
Buffer
HDMA Transfer
Transfer
AMBA
Burst
AT91SAM9R64/RL64 Preliminary
Buffer
Transfer
AMBA
Single
DMA Transfer
Level
Buffer Transfer
Level
AMBA Transfer
Level
571
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