AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 886

• Manufacturer Part Number: AT91SAM9R64-CU-999
• Description: IC MCU ARM9 64K SRAM 144LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

47.2.6
47.2.6.1
47.2.6.2
47.2.6.3
47.2.6.4
886
AT91SAM9R64/RL64 Preliminary
Serial Synchronous Controller (SSC)
SSC: Transmitter Limitations in Slave Mode
SSC: Periodic Transmission Limitations in Master Mode
SSC: Unexpected RK clock cycle when RK outputs a clock during data transfer
SSC: Incorrect first RK clock cycle when RK outputs a clock during data transfer
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
None.
If Last Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent.
None.
When the SSC receiver is used in the following configuration:
then, at the end of the data, the RK pin is set in high impedance which may be interpreted as an
unexpected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used in the following configuration:
• the internal clock divider is used (CKS =0 and DIV different from 0),
• RK pin set as output and provides the clock during data transfer (CKO=2)
• data sampled on RK falling edge (CKI =0)
• RX clock is divided clock (CKS =0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO=2)
• data sampled on RK falling edge (CKI =0)
;prepare power down command
;prepare proc_reset and periph_reset
;perform power down command
;perform proc_reset and periph_reset (in the ARM pipeline)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
LDR r0, =AT91C_SDRAMC_LPR
LDR r1, =2
LDR r2, =AT91C_RSTC_RCR
LDR r3, =0xA5000005
STR r1, [r0]
STR r3, [r2]
END
6289C–ATARM–28-May-09