AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 754

• Manufacturer Part Number: AT91SAM9R64-CU-999
• Description: IC MCU ARM9 64K SRAM 144LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

41.4.9
41.4.10
41.4.11
754
AT91SAM9R64/RL64 Preliminary
Speed Identification
USB V2.0 High Speed Global Interrupt
Endpoint Interrupts
The high speed reset is managed by the hardware.
At the connection, the host makes a reset which could be a classic reset (full speed) or a high
speed reset.
At the end of the reset process (full or high), the ENDRESET interrupt is generated.
Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of
the device.
Interrupts are defined in
in
Interrupts are enabled in UDPHS_IEN (see
and individually masked in UDPHS_EPTCTLENBx (see
Control Enable
.
Table 41-4.
SHRT_PCKT
BUSY_BANK
NAK_OUT
NAK_IN/ERR_FLUSH
STALL_SNT/ERR_CRISO/ERR_NB_TRA
RX_SETUP/ERR_FL_ISO
TX_PK_RD /ERR_TRANS
TX_COMPLT
RX_BK_RDY
ERR_OVFLW
MDATA_RX
DATAX_RX
Section 41.5.4 ”UDPHS Interrupt Status Register”
Endpoint Interrupt Source Masks
Register”).
Section 41.5.3 ”UDPHS Interrupt Enable Register”
Section 41.5.3 ”UDPHS Interrupt Enable
Short Packet Interrupt
Busy Bank Interrupt
NAKOUT Interrupt
NAKIN/Error Flush Interrupt
Stall Sent/CRC error/Number of Transaction Error
Interrupt
Received SETUP/Error Flow Interrupt
TX Packet Read/Transaction Error Interrupt
Transmitted IN Data Complete Interrupt
Received OUT Data Interrupt
Overflow Error Interrupt
MDATA Interrupt
DATAx Interrupt
(UDPHS_INTSTA).
Section 41.5.17 ”UDPHS Endpoint
6289C–ATARM–28-May-09
(UDPHS_IEN) and
Register”)