LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 17

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
6.6 External Bus Interface (EBI)
6.7 Internal Static ROM (ISROM)
The EBI module acts as multiplexer with arbitration between the NAND flash and the
SDRAM/SRAM memory modules connected externally through the MPMC.
The main purpose for using the EBI module is to save external pins. However only data
and address pins are multiplexed. Control signals towards and from the external memory
devices are not multiplexed.
Table 7.
The internal static ROM is used to store the boot code of the LPC3141/3143. After a reset,
the ARM processor will start its code execution from this memory.
The LPC3143 ROM memory has the following features:
Module
External SRAM0
External SRAM1
External SDRAM0 0x3000 0000
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– output enable and write enable delays
– extended wait
One chip select for synchronous memory and two chip selects for static memory
devices.
Power-saving modes.
Dynamic memory self-refresh mode supported.
Controller support for 2 k, 4 k, and 8 k row address synchronous memory parts.
Support for all AHB burst types.
Little and big endian support.
Support for the External Bus Interface (EBI) that enables the memory controller pads
to be shared.
Supports secure booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART,
and USB (DFU class) interfaces.
Supports SHA1 hash checking on the boot image.
Supports non-secure boot from UART and USB (DFU class) interfaces during
development. Once AES key is programmed in OTP, only secure boot is allowed
through UART and USB.
Supports secure booting from managed NAND devices such as moviNAND, iNAND,
eMMC-NAND and eSD-NAND using SD/MMC boot mode.
Contains pre-defined MMU table (16 kB) for simple systems.
Memory map of the external SRAM/SDRAM memory modules
All information provided in this document is subject to legal disclaimers.
Maximum address space
0x2000 0000
0x2000 0000
0x2002 0000
0x2002 0000
Rev. 0.16 — 27 May 2010
0x2000 FFFF
0x2001 FFFF
0x2002 FFFF
0x2003 FFFF
0x37FF FFFF
Data width
8 bit
16 bit
8 bit
16 bit
16 bit
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
64 kB
128 kB
64 kB
128 kB
128 MB
Device size
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