LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 20

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
6.11 DMA controller
The DMA controller can perform DMA transfers on the AHB without using the CPU.
This module has the following features:
Table 9:
Peripheral name
NAND flash controller/AES decryption engine
SPI
MCI
LCD interface
UART
I
2
•
•
•
•
•
•
•
•
•
•
•
•
C0/1-bus interfaces
Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
Contains UTMI+ compliant transceiver (PHY).
Supports interrupts.
This module has its own, integrated DMA engine.
Supported transfer types:
Memory to memory copy
– Memory can be copied from the source address to the destination address with a
Memory to peripheral
– Data is transferred from incrementing memory to a fixed address of a peripheral.
Peripheral to memory
– Data is transferred from a fixed address of a peripheral to incrementing memory.
Supports single data transfers for all transfer types.
Supports burst transfers for memory to memory transfers. A burst always consists of
multiples of 4 (32 bit) words.
The DMA controller has 12 channels.
Scatter-gather is used to gather data located at different areas of memory. Two
channels are needed per scatter-gather action.
Supports byte, half-word, and word transfers and correctly aligns them over the AHB
bus.
Compatible with ARM flow control for single requests, last single requests, terminal
count info, and DMA clearing.
Supports swapping endian property of the transported data.
specified length, while incrementing the address for both the source and
destination.
The flow is controlled by the peripheral.
The flow is controlled by the peripheral.
Peripherals that support DMA
All information provided in this document is subject to legal disclaimers.
Rev. 0.16 — 27 May 2010
[1]
Supported transfer types
Memory to memory
Memory to peripheral and peripheral to memory
Memory to peripheral and peripheral to memory
Memory to peripheral
Memory to peripheral and peripheral to memory
Memory to peripheral and peripheral to memory
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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