LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 25

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
6.15 Clock Generation Unit (CGU)
The clock generation unit generates all clock signals in the system and controls the reset
signals for all modules. The structure of the CGU is shown in
generated by the CGU belongs to one of the domains. Each clock domain is fed by a
single base clock that originates from one of the available clock sources. Within a clock
domain, fractional dividers are available to divide the base clock to a lower frequency.
Within most clock domains, the output clocks are again grouped into one or more
subdomains. All output clocks within one subdomain are either all generated by the same
fractional divider or they are connected directly to the base clock. Therefore all output
clocks within one subdomain have the same frequency and all output clocks within one
clock domain are synchronous because they originate from the same base clock.
The CGU reference clock is generated by the external crystal. Furthermore the CGU has
several Phase Locked Loop (PLL) circuits to generate clock signals that can be used for
system clocks and/or audio clocks. All clock sources, except the output of the PLLs, can
be used as reference input for the PLLs.
This module has the following features:
•
•
•
•
Advanced features to optimize the system for low power:
– All output clocks can be disabled individually for flexible power optimization.
– Some modules have automatic clock gating: they are only active when (bus)
– Variable clock scaling for automatic power optimization of the AHB bus (high clock
– Clock wake-up feature: module clocks can be programmed to be activated
Supports five clock sources:
– Reference clock generated by the oscillator with an external crystal.
– Pins I2SRX_BCK0, I2SRX_WS0, I2SRX_BCK1 and I2SRX_WS1 are used to input
Supports two PLLs:
– System PLL generates programmable system clock frequency from its reference
– I
Highly flexible switchbox to distribute the signals from the clock sources to the module
clocks.
– Each clock generated by the CGU is derived from one of the base clocks and
access to the module is required.
frequency when the bus is active, low clock frequency when the bus is idle).
automatically on the basis of an event detected by the event router (see also
Section
activated automatically when a button is pressed.
external clock signals (used for generating audio frequencies in I2SRX slave
mode, see also
input.
from its reference input.
Remark: Both the System PLL and the I
based on their (individual) reference clocks. The reference clocks can be
programmed to the oscillator clock or one of the external clock signals.
optionally divided by a fractional divider.
2
S/Audio PLL generates programmable audio clock frequency (typically 256 × fs)
6.19). For example, all clocks (including the core/bus clocks) are off and
All information provided in this document is subject to legal disclaimers.
Rev. 0.16 — 27 May 2010
Section
6.4).
2
S/Audio PLL generate their frequencies
LPC3141/3143
Figure
6. Each output clock
© NXP B.V. 2010. All rights reserved.
25 of 74