LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 8

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
Table 4.
Pin names with prefix m are multiplexed pins. See
LPC3141_3143
Preliminary data sheet
Pin name
Serial Peripheral Interface (SPI)
SPI_CS_OUT0
SPI_SCK
SPI_MISO
SPI_MOSI
SPI_CS_IN
Digital power supply
VDDI
VSSI
Peripheral power supply
VDDE_IOA
VDDE_IOB
VDDE_IOC
VSSE_IOA
VSSE_IOB
[4]
[4]
[4]
Pin description
[4]
[4]
BGA
Ball
A7
A8
C8
B7
B8
H3;
L7;
L12;
C12;
C6
A11;
C7;
D12;
G4;
L6;
L11
B2;
E5;
F5;
G5;
H5
L4;
M5;
M7;
M9
C13;
D5;
D7;
E8;
G12;
L10;
K11
C3;
C4;
E4;
F4;
H4;
K3
M3;
M4;
M6;
M8
…continued
Digital
I/O
level
[1]
SUP3
SUP3
SUP3
SUP3
SUP3
SUP1
SUP4
SUP8
SUP3
-
-
All information provided in this document is subject to legal disclaimers.
Application
function
DO
DIO
DIO
DIO
DI
Supply
Ground
Supply
Supply
Supply
Ground
Ground
Rev. 0.16 — 27 May 2010
Table 10
Pin
state
after
reset
O
I
I
I
I
-
-
-
-
-
-
-
for pin function selection of multiplexed pins.
[2]
Cell type
[3]
DIO4
DIO4
DIO4
DIO4
DIO4
CS2
CG2
PS1
PS1
PS1
PG1
PG1
Description
SPI chip select output (master).
SPI clock input (slave)/clock output (master).
SPI data input (master)/data output (slave).
SPI data output (master)/data input (slave).
SPI chip select input (slave).
Digital core supply.
Digital core ground.
Peripheral supply for NAND flash interface.
Peripheral supply for SDRAM/LCD.
Peripheral supply.
-
-
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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