LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 49

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
Fig 13. LCD timing (Motorola 6800 mode)
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:12] (4 bit mode)
mLCD_DB[15:12] (4 bit mode)
mLCD_DB[15:8] (8 bit mode),
mLCD_DB[15:8] (8 bit mode),
9.1.2 Motorola 6800 mode
mLCD_RW_WR
mLCD_E_RD
Table 16.
C
[1]
Symbol
t
t
t
t
t
t
t
t
t
t
mLCD_CSB
su(A)
h(A)
cy(a)
r
f
su(D)
h(D)
d(QV)
dis(Q)
w(en)
L
mLCD_RS,
= 25 pF, T
Timing is derived from the LCD Interface Control Register fields: INVERT_CS = 1; MI = 1; PS = 0;
INVERT_E_RD = 0. See the LPC314x user manual.
Dynamic characteristics: LCD controller in Motorola 6800 mode
Parameter
address set-up time
address hold time
access cycle time
rise time
fall time
data input set-up time
data input hold time
data output valid delay time
data output disable time
enable pulse width
amb
=
All information provided in this document is subject to legal disclaimers.
−
40
°
C to +85
Rev. 0.16 — 27 May 2010
t
su(A)
t
r
°
C, unless otherwise specified; V
t
d(QV)
Conditions
read cycle
write cycle
t
w(en)
t
su(D)
t
f
t
cy(a)
t
t
[1]
h(D)
h(A)
t
dis(Q)
Min
-
-
-
2
2
<tbd>
<tbd>
-
-
-
-
LPC3141/3143
DD(IO)
Typ
1 × LCDCLK
2 × LCDCLK
5 × LCDCLK
-
-
-
-
−1 × LCDCLK
2 × LCDCLK
2 × LCDCLK
2 × LCDCLK
= 1.8 V and 3.3 V (SUP8).
© NXP B.V. 2010. All rights reserved.
read access
write access
002aae208
Max
-
-
-
5
5
-
-
-
-
-
-
49 of 74
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns