LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 57

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
9.4 NAND flash memory controller
Table 20.
T
[1]
[2]
[3]
Symbol
t
t
t
t
t
t
t
t
t
t
REH
RP
WH
WP
CLS
CLH
ALS
ALH
CS
CH
amb
Fig 19.
T
See registers NandTiming1 and NandTiming2 in the LPC314x user manual.
Each timing parameter can be set from 7 nand_clk clock cycles to 1 nand_clk clock cycle. (A programmed
zero value is treated as a one).
=
HCLK
−
40
= 1 / NANDFLASH_NAND_CLK, see LPC314x user manual.
NAND flash controller write and read timing
°
Dynamic characteristics of the NAND Flash memory controller
C to +85
Parameter
RE HIGH hold time
RE pulse width
WE HIGH hold time
WE pulse width
CLE set-up time
CLE hold time
ALS set-up time
ALE hold time
CE set-up time
CE hold time
EBI_DQM_0_NOE
All information provided in this document is subject to legal disclaimers.
EBI_A_1_CLE
EBI_A_0_ALE
mNAND_NCS
°
EBI_NWE
C, unless otherwise specified.
Rev. 0.16 — 27 May 2010
t
ALS
t
CLS
t
CS
t
WP
[1][2][3]
[1][2][3]
[1][2][3]
[1][2][3]
[1][2][3]
[1][2][3]
[1][2][3]
[1][2][3]
[1][2][3]
[1][2][3]
t
WH
t
CLH
Typical
T
T
T
T
T
T
T
T
T
T
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
t
ALH
× (TREH)
× (TRP)
× (TWH)
× (TWP)
× (TCLS)
× (TCLH)
× (TALS)
× (TALH)
× (TCS)
× (TCH)
t
RP
LPC3141/3143
t
REH
002aae353
t
CH
© NXP B.V. 2010. All rights reserved.
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Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns