LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 69

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
13. Abbreviations
LPC3141_3143
Preliminary data sheet
Table 30.
Acronym
A/D
ADC
AES
AHB
AMBA
APB
ATA
BIU
CBC
CE
CGU
CRC
DFU
DMA
DRM
DSP
EBI
ECC
EOP
ESD
FIFO
FPGA
GF
IOCONFIG
IOM
IrDA
ISRAM
ISROM
JTAG
LSB
MCI
MCU
MMC
MPMC
OTG
PCM
PHY
PLL
PWM
Abbreviations
All information provided in this document is subject to legal disclaimers.
Description
Analog-to-Digital
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced High-performance Bus
Advanced Microcontroller Bus Architecture
ARM Peripheral Bus
Advanced Transport Architecture
Bus Interface Unit
Cipher Block Chaining
Consumer Electronics
Clock Generation Unit
Cyclic Redundancy Check
Device Firmware Upgrade
Direct Memory Access
Digital Rights Management
Digital Signal Processing
External Bus Interface
Error Correction Code
End Of Packet
Electrostatic Discharge
First In, First Out
Field Programmable Gate Array
Galois Field
Input Output Configuration
ISDN Oriented Modular
Infrared Data Association
Internal Static RAM
Internal Static ROM
Joint Test Action Group
Least Significant Bit
Memory Card Interface
Microcontroller Unit
Multi-Media Card
Multi-Port Memory Controller
On-The-Go
Pulse Code Modulation
Physical Layer
Phase Locked Loop
Pulse Width Modulation
Rev. 0.16 — 27 May 2010
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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