LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 26

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
Fig 6. CGU block diagram
EXTERNAL
CRYSTAL
I2SRX_BCK1
I2SRX_BCK0
I2SRX_WS0
I2SRX_WS1
The LPC3141/3143 has 11 clock domains (n = 11). The number of fractional dividers m depends on the clock domain.
clock resources
6.16 Watchdog Timer (WDT)
OSCILLATOR
The watchdog timer can be used to generate a system reset if there is a CPU/software
crash. In addition the watchdog timer can be used as an ordinary timer.
how the watchdog timer module is connected in the system.
This module has the following features:
•
•
•
•
– Each base clock can be programmed to have any one of the clock sources as an
– Fractional dividers can be used to divide a base clock by a fractional number to a
– Fractional dividers support clock stretching to obtain a (near) 50% duty cycle
Register interface to reset all modules under software control.
Based on the input of the Watchdog timer (see also
generate a system-wide reset in the case of a system stall.
In the event of a software or hardware failure, generates a chip-wide reset request
when its programmed time-out period has expired (output m1).
Watchdog counter can be reset by a periodical software trigger.
input clock.
lower clock frequency.
output clock.
All information provided in this document is subject to legal disclaimers.
Rev. 0.16 — 27 May 2010
I
2
SYSTEM
S/AUDIO
PLL
PLL
SWITCHBOX
CLOCK DOMAIN 0
CLOCK DOMAIN n
BASE
subdomain clocks
Section
FRACTIONAL
FRACTIONAL
DIVIDER m
LPC3141/3143
DIVIDER 0
6.16), the CGU can
© NXP B.V. 2010. All rights reserved.
Figure 7
clock outputs
002aae916
to modules
shows
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