P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 28

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
13.3
The internal interface between the P8xC592's CPU and
on-chip CAN-controller is achieved via the following four
SFRs (see Fig.13):
Additionally, the DMA-logic allows a high-speed data
exchange between the CAN-controller and the CPU's
on-chip MAIN RAM. For more information, see
Section 13.5.15 “Handling of the CPU-CAN interface”.
13.4
The P8xC592 CAN-controller contains all necessary
hardware for high performance serial network
communications (see Fig.14 and Table 29).
1996 Jun 27
handbook, full pagewidth
CANADR, to point to a register of the CAN-controller
CANDAT, to read or write data
CANCON, to read interrupt flags and to write commands
CANSTA, to read status information and to write DMA
pointer.
8-bit microcontroller with on-chip CAN
Interface between CPU and CAN
Hardware blocks of the CAN-controller
MAIN
RAM
CPU
Fig.13 Interface between CPU and CAN-controller.
internal
bus
DMA bus
4 special function
CANADR
CANDAT
CANCON
CANSTA
registers
28
It controls the communication flow through the area
network using the CAN-protocol. The CAN-controller
meets the following automotive requirements:
Short message length
Bus access priority, determined by the message
identifier
Powerful error handling capability
Configuration flexibility to allow area network expansion
Guaranteed latency time for urgent messages;
– The latency time defines the period between the
DBH
DAH
D9H
D8H
initiation (Transmission Request) and the start of the
transmission on the bus. The latency time strongly
depends on a large variety of bus-related conditions.
In the case of a message being transmitted on the
bus and one distortion, the latency time can be up to
149 bit times (worst case). For more information see
Chapter 22 “CAN application information”.
LOGIC
DMA
MGA158
ADDRESS
DATA
CONTROLLER
CAN
Product specification
P8xC592