P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 48

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
13.5.15.1 Special Function Register CANADR
Table 59 SFR CANADR (address DBH)
Table 60 Description of the CANADR bits
13.5.15.2 Special Function Register CANDAT
CANDAT is implemented as a read/write register.
Table 61 SFR CANDAT (address DAH)
Table 62 Description of the CANADR bits
1996 Jun 27
CANADR is implemented as a read/write register.
BIT SYMBOL
BIT SYMBOL
to
7
6
5
4
3
2
1
0
7
0
8-bit microcontroller with on-chip CAN
CAND7
DMA
DMA
AutoInc
CANA4
CANA3
CANA2
CANA1
CANA0
CAND7
to
CAND0
7
7
DMA-logic controlled via bit CANADR.7 (see Section 13.5.17).
Reserved.
Auto Address Increment mode controlled via bit CANADR.5 (see Section 13.5.16).
The five least significant bits CANADR.4 to CANADR.0 define the address of one of the
CAN-controller internal registers to be accessed via CANDAT. For instance, after an external
hardware (e.g. power-on) reset CANADR contains the value 64H, and hence the CPU accesses
(read/write) the Acceptance Code register of the CAN-controller, via the SFR CANDAT.
The SFR CANDAT appears as a port to the CAN-controller internal register (memory location) being
selected by CANADR. Reading or writing CANDAT is effectively an access to that CAN-controller
internal register, which is selected by CANADR.
CAND6
6
6
AutoInc
CAND5
5
5
CAND4
CANA4
4
4
48
FUNCTION
FUNCTION
CANA3
CAND3
3
3
CAND2
CANA2
2
2
CANA1
CAND1
1
1
Product specification
P8xC592
CAND0
CANA0
0
0