P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 69

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
15.4
The instruction that sets bit PCON.1 to HIGH, is the last
one executed before entering the Power-down mode. In
Power-down mode the oscillator of the P8xC592 is
stopped. If the CAN-controller is in use, it is recommended
to set it into Sleep mode before entering Power-down
mode. However, setting PCON.1 to HIGH also sets the
Sleep bit (CAN-controller Command Register bit 4) to
HIGH.
The P8xC592 leaves Power-down mode either by a
hardware reset or by a CAN Wake-Up interrupt
(due to activity on the CAN-bus),
if the SIO1 (CAN) interrupt source is enabled
(contents of register IEN0 = 1X1XXXXXB).
Table 82 Status of external pins during Idle and Power-down modes
Note
1. If the port pins P1.6 and P1.7 are used as the CAN transmitter outputs (CTX0 and CTX1), then during Sleep and
1996 Jun 27
Idle
Power-down
8-bit microcontroller with on-chip CAN
Power-down mode these pins output a ‘recessive’ level (see Sections 13.5.2 and 13.5.11).
MODE
Power-down Mode
internal
external
internal
external
PROGRAM
ALE
1
1
0
0
PSEN
1
1
0
0
port data
floating
port data
floating
PORT0
69
A hardware reset affects the whole P8xC592, but leaves
the contents of the on-chip RAM unchanged
(CAN-controller-and CPU's SFRs are reset, see
Section 13.5.2, Chapter 17 and Table 40). A CAN
Wake-Up interrupt during Power-down mode causes a
reset output pulse with a width of 6144 machine cycles
(4.6 ms with f
the CAN-controller of the P8xC592 is reset (i.e. the
contents of all CAN-controller registers are preserved).
A capacitance connected to the RST pin can be used to
lengthen the internally generated reset pulse. If the pulse
exceeds 8192 machine cycles, the CAN-controller part is
reset too.
port data
port data
port data
port data
PORT1
(1)
port data
address
port data
port data
CLK
PORT2
= 16 MHz). All hardware except that for
port data
port data
port data
port data
PORT3
port data
port data
port data
port data
PORT4
Product specification
P8xC592
PWM0/
PWM1
1
1
1
1