P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 37

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
13.5.5
The contents of the Status Register reflects the status of the CAN-controller. The Status Register appears to the CPU
as a read only memory.
Table 36 Status Register (address 2)
Table 37 Description of the SR bits
1996 Jun 27
BIT SYMBOL
7
6
5
4
3
2
1
0
8-bit microcontroller with on-chip CAN
BS
BS
ES
TS
RS
TCS
TBS
DO
RBS
7
S
TATUS
R
Bus Status (note 1). If the value of BS is:
Error Status. If the value of ES is:
Transmit Status (note 2). If the value of TS is:
Receive Status (note 2). If the value of RS is:
Transmission Complete Status (note 3). If the value of TCS is:
Transmit Buffer Access (note 3). If the value of TBS is:
Data Overrun (note 4). If the value of DO is:
Receive Buffer Status (note 5). If the value of RBS is
EGISTER
HIGH (Bus-OFF), then the CAN-controller is not involved in bus activities.
LOW (Bus-ON), then the CAN-controller is involved in bus activities.
HIGH (error), then at least one of the Error Counters (see Section 13.6.10) has reached the
CPU Warning limit.
LOW (ok), then both Error Counters have not reached the warning limit.
HIGH (transmit), then the CAN-controller is transmitting a message.
LOW (idle), then no message is transmitted.
HIGH (receive), then the CAN-controller is receiving a message.
LOW (idle), then no message is received.
HIGH (complete), then last requested transmission has been successfully completed.
LOW (incomplete), then previously requested transmission is not yet completed.
HIGH (released), then the CPU may write a message into the TBF.
LOW (locked), then the CPU cannot access the Transmit Buffer. A message is either waiting for
transmission or is in the process of being transmitted.
HIGH (overrun), then both Receive Buffers are full and the first byte of another message should be
stored.
LOW (absent), then no data overrun has occurred since the Clear Overrun command was given.
HIGH (full), then this bit is set when a new message is available.
LOW (empty), then no message has become available since the last Release Receive Buffer
command bit was set.
ES
6
(SR)
TS
5
RS
4
37
FUNCTION
TCS
3
TBS
2
DO
1
Product specification
P8xC592
RBS
0