P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 29

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
Table 29 Hardware blocks of the CAN-controller (see Fig.14)
1996 Jun 27
Interface Management Logic IML
Transmit Buffer
Receive Buffers (0 and 1)
Bit Stream Processor
Bit Timing Logic
Transceiver Control Logic
Error Management Logic
handbook, full pagewidth
8-bit microcontroller with on-chip CAN
NAME
address
data
Fig.14 Block diagram of the P8xC592 on-chip CAN-controller.
BLOCK
TBF
RBF0
RBF1
BSP
BTL
TCL
EML
Interprets commands from the CPU, allocates the message buffers
(TBF, RBF0 and RBF1) and provides interrupts and status information to the
microcontroller.
10 bytes memory into which the CPU writes messages which are to be
transmitted over the CAN network.
RBF0 and RBF1 are each 10 bytes memories which are alternatively used to
store messages received from the CAN network.
The CPU can process one message while another is being received.
Is a sequencer, controlling the data stream between the Transmit Buffer,
Receive Buffers (parallel data) and the CAN-bus (serial data).
Synchronizes the CAN-controller to the bitstream on the CAN-bus.
Controls the output driver.
Performs the error confinement according to the CAN-protocol.
MANAGEMENT
INTERFACE
BUFFER 1
TRANSMIT
BUFFER 0
RECEIVE
RECEIVE
BUFFER
LOGIC
ON - CHIP
29
CONTROLLER
TRANSCEIVER
MANAGEMENT
PROCESSOR
CAN
BIT STREAM
BIT TIMING
DESCRIPTION
ERROR
LOGIC
LOGIC
LOGIC
2
2
MGA159
CRX0
CRX1
CTX0
CTX1
and
and
Product specification
P8xC592