P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 42

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
13.5.9
The contents of Bus Timing Register 0 defines the values
of the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW).
Table 45 Bus Timing Register 0 (address 6)
Table 46 Description of the BTR0 bits
1996 Jun 27
BIT SYMBOL
7
6
5
4
3
2
1
0
8-bit microcontroller with on-chip CAN
SJW.1
SJW.1
SJW.0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
BRP.0
7
B
US
T
IMING
Synchronization Jump Width. To compensate for phase shifts between clock oscillators of different
bus controllers, any bus controller must resynchronize on any relevant signal edge of the current
transmission. The synchronization jump width defines the maximum number of clock cycles a bit
period may be shortened or lengthened by one resynchronization:
Baud Rate Prescaler. The period of the system clock t
individual bit timing.The system clock is calculated using the following equation:
Where t
t
t
SJW.0
SJW
SCL
R
6
EGISTER
=
=
CLK
2t
t
SCL
CLK
= time period of the P8xC592 oscillator.
0 (BTR0)
2SJW.1
32BRP.5
BRP.5
5
+
˙˙
SJW.0
+
16BRP.4
BRP.4
+
4
1
.
+
8BRP.3
42
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).
For further information on bus timing, see
Sections 13.5.10 and 13.5.18.
FUNCTION
BRP.3
+
3
4BRP.2
SCL
+
is programmable and determines the
2BRP.1
BRP.2
2
+
BRP.0
BRP.1
+
1
1
Product specification
.
P8xC592
BRP.0
0