P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 49

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
13.5.15.3 Special Function Register CANCON
Table 63 SFR CANCON in Read access (address D9H)
Table 64 Description of the CANCON bits in Read access
When reading CANCON the Interrupt Register of the CAN-controller is accessed.
Table 65 SFR CANCON in Write access (address D9H)
Table 66 Description of the CANCON bits in Write access
When writing to CANCON then the Command Register of the CAN-controller is accessed.
1996 Jun 27
8-bit microcontroller with on-chip CAN
RX0A
BIT
BIT
7
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
1
0
WUI
OI
EI
TI
RI
RX0A
RX1A
WUM
SLP
COS
RRB
AT
TR
SYMBOL
SYMBOL
RX1A
6
6
Reserved; bits are read as HIGH.
Wake-Up Interrupt (see Table 39).
Overrun Interrupt (see Table 39).
Error Interrupt (see Table 39).
Transmit Interrupt (see Table 39).
Receive Interrupt (see Table 39).
RX0 Active (see Table 34).
RX1 Active (see Table 34).
Wake-Up Mode (see Table 34).
Sleep (see Table 34).
Clear Overrun Status (see Table 34).
Release Receive Buffer (see Table 34).
Abort Transmission (see Table 34).
Transmission Request (see Table 34).
WUM
5
5
WUI
SLP
4
4
49
COS
OI
3
3
FUNCTION
FUNCTION
RRB
EI
2
2
AT
TI
1
1
Product specification
P8xC592
TR
RI
0
0