P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 87

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
handbook, full pagewidth
1996 Jun 27
8-bit microcontroller with on-chip CAN
are valid when
during a write
RD or WR are
during a read
from external
data memory
data memory
external data
The Port 5 input buffers have a maximum propagation delay of 300 ns.
As a result Port 5 sample time begins 300 ns before state S5 and ends
when S5 has finished.
dotted lines
only active
to external
only active
program
memory
memory
external
read or
write of
active
fetch
XTAL1
INPUT
ALE
PSEN
RD
WR
BUS
(PORT 0)
PORT 2
BUS
(PORT 0)
PORT 2
PORT
OUTPUT
PORT
INPUT
SERIAL
PORT
CLOCK
inst.
inst.
P1 P2
in
in
S1
P1 P2
address
address
A0 - A7
A0 - A7
S2
address A8 - A15
address A8 - A15
one machine cycle
P1 P2
S3
old data
Fig.30 Instruction cycle timing.
inst.
inst.
P1 P2
in
in
S4
sampling time of I/O port pins during input (including INT0 and INT1)
P1 P2
address
address
A0 - A7
A0 - A7
S5
87
address A8 - A15
P1 P2
S6
address A8 - A15 or Port 2 out
inst.
P1 P2
in
data output or data input
S1
P1 P2
address
A0 - A7
S2
address A8 - A15
one machine cycle
P1 P2
S3
new data
inst.
P1 P2
in
S4
Product specification
P1 P2
address
address
A0 - A7
A0 - A7
S5
address A8 - A15
address A8 - A15
P8xC592
P1 P2
MGA180
S6