MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 170

• Manufacturer Part Number: MC908MR32CFUE
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR32CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 6
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Communications Interface Module (SCI)
ENSCI — Enable SCI Bit
TXINV — Transmit Inversion Bit
M — Mode (Character Length) Bit
WAKE — Wakeup Condition Bit
ILTY — Idle Line Type Bit
PEN — Parity Enable Bit
PTY — Parity Bit
170
This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
This read/write bit determines whether SCI characters are eight or nine bits long. See
ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the
M bit.
This read/write bit determines which condition wakes up the SCI: a 1 (address mark) in the most
significant bit (MSB) position of a received character or an idle condition on the PTF4/RxD pin. Reset
clears the WAKE bit.
This read/write bit determines when the SCI starts counting 1s as idle character bits. The counting
begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string
of 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after
the stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
Reset clears the ILTY bit.
This read/write bit enables the SCI parity function. See
inserts a parity bit in the most significant bit position. See
This read/write bit determines whether the SCI generates and checks for odd parity or even parity. See
Table
1 = SCI enabled
0 = SCI disabled
1 = Transmitter output inverted
0 = Transmitter output not inverted
1 = 9-bit SCI characters
0 = 8-bit SCI characters
1 = Address mark wakeup
0 = Idle line wakeup
1 = Idle character bit count begins after stop bit.
0 = Idle character bit count begins after start bit.
1 = Parity function enabled
0 = Parity function disabled
1 = Odd parity
0 = Even parity
13-4. Reset clears the PTY bit.
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
NOTE
NOTE
Table
Figure
13-4. When enabled, the parity function
13-4. Reset clears the PEN bit.
Freescale Semiconductor
Table
13-4. The