MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 200

• Manufacturer Part Number: MC908MR32CFUE
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR32CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 6
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Peripheral Interface Module (SPI)
The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The
clock phase and polarity should be identical for the master SPI device and the communicating slave
device. In some cases, the phase and polarity are changed between transmissions to allow a master
device to communicate with peripheral slaves having different requirements.
15.5.2 Transmission Format When CPHA = 0
Figure 15-5
replacement for data sheet parametric information.Two waveforms are shown for SPSCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
15.6.2 Mode Fault
the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used
to start the slave data transmission. The slave’s SS pin must be toggled back to high and then low again
between each byte transmitted as shown in
200
shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a
CAPTURE STROBE
MASTER SS
FOR REFERENCE
MISO/MOSI
SPSCK, CPOL = 0
SPSCK, CPOL = 1
Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing
the SPI enable bit (SPE).
SLAVE SS
SLAVE SS
SPSCK CYCLE #
CPHA = 0
CPHA = 1
FROM MASTER
SS, TO SLAVE
FROM SLAVE
Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore,
MOSI
MISO
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Figure 15-5. Transmission Format (CPHA = 0)
MSB
MSB
BYTE 1
1
Figure 15-6. CPHA/SS Timing
BIT 6
BIT 6
2
Figure
BIT 5
BIT 5
3
NOTE
15-6.
BYTE 2
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
BYTE 3
BIT 1
BIT 1
7
LSB
LSB
8
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