MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 72

IC MCU 8MHZ 32K FLASH 64-QFP

MC908MR32CFUE

Manufacturer Part Number
MC908MR32CFUE
Description
IC MCU 8MHZ 32K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908MR32CFUE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
44
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI/SPI
Maximum Clock Frequency
8.2 MHz
Number Of Programmable I/os
44
Number Of Timers
6
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Clock Generator Module (CGM)
The K factor in the equations is derived from internal PLL parameters. K
is configured in acquisition mode, and K
See
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. See
cycles, n
before exiting acquisition mode. A certain number of clock cycles, n
PLL is within the lock mode entry tolerance, ∆
multiple of n
the average frequency over the entire measurement period must be within the specified tolerance, the
total time usually is longer than t
In manual mode, it is usually necessary to wait considerably longer than t
clock (see
Influences on Reaction Time
72
4.3.2.2 Acquisition and Tracking
ACQ
4.3.3 Base Clock Selector
ACQ
, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆
The inverse proportionality between the lock time and the reference
frequency.
/f
RDV
, and the acquisition to lock time, t
4.3.2.3 Manual and Automatic PLL Bandwidth Modes
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
may slow the lock time considerably.
Lock
as calculated in the previous example.
Modes.
Circuit) because the factors described in
TRK
t
ACQ
t
AL
t
Lock
is the K factor when the PLL is configured in tracking mode.
=
Lock
=
V
-------------- -
=
NOTE
f
V
-------------- -
. Therefore, the acquisition time, t
RDV
f
DDA
RDV
DDA
t
ACQ
AL
------------- -
K
+
-------------- -
K
, is an integer multiple of n
TRK
t
4
ACQ
AL
8
TRK
ACQ
, is required to ascertain that the
Lock
is the K factor when the PLL
before selecting the PLL
A certain number of clock
4.8.2 Parametric
TRK
Freescale Semiconductor
ACQ
/f
, is an integer
RDV
. Also, since
TRK
,

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