MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 68

• Manufacturer Part Number: MC908MR32CFUE
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR32CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 6
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clock Generator Module (CGM)
XLD — Crystal Loss Detect Bit
PBWC[3:0] — Reserved for Test
4.5.3 PLL Programming Register
The PLL programming register (PPG) contains the programming information for the modulo feedback
divider and the programming information for the hardware configuration of the VCO.
MUL[7:4] — Multiplier Select Bits
68
When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the
crystal reference frequency is active or not. To check the status of the crystal reference, follow these
steps:
The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive
CGMOUT. When BCS is clear, XLD always reads as logic 0.
These bits enable test functions not available in user mode. To ensure software portability from
development systems to user applications, software should write 0s to PBWC[3:0] whenever writing to
PBWC.
These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier,
N. See
configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to
give a default multiply value of 6.
1. Write a logic 1 to XLD.
2. Wait N × 4 cycles. (N is the VCO frequency multiplier.)
3. Read XLD.
1 = Crystal reference is not active.
0 = Crystal reference is active.
4.3.2.1 PLL Circuits
Address: $005E
Reset:
Read:
Write:
MUL7:MUL6:MUL5:MUL4
MUL7
Bit 7
0
Table 4-2. VCO Frequency Multiplier (N) Selection
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Figure 4-7. PLL Programming Register (PPG)
0000
0001
0010
0011
1101
1110
1111
and
MUL6
6
1
4.3.2.4 Programming the
MUL5
5
1
MUL4
4
0
VCO Frequency Multiplier (N)
VRS7
PLL. A value of $0 in the multiplier select bits
3
0
VRS6
13
14
15
1
1
2
3
2
1
VRS5
1
1
Freescale Semiconductor
VRS4
Bit 0
0