MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 192

• Manufacturer Part Number: MC908MR32CFUE
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR32CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 6
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Integration Module (SIM)
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
14.7.2 SIM Reset Status Register
The SIM reset status register (SRSR) contains six flags that show the source of the last reset. Clear the
SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the
register.
POR — Power-On Reset Bit
PIN — External Reset Bit
COP — Computer Operating Properly Reset Bit
ILOP — Illegal Opcode Reset Bit
ILAD — Illegal Address Reset Bit (opcode fetches only)
MENRST — Forced Monitor Mode Entry Reset Bit
LVI — Low-Voltage Inhibit Reset Bit
192
1 = Last reset caused by POR circuit
0 = Read of SRSR
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
1 = Last reset caused by COP counter
0 = POR or read of SRSR
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
1 = Last reset caused by the MENRST circuit
0 = POR or read of SRSR
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
Address: $FE01
Reset:
Read:
Write:
BIt 7
POR
R
R
1
Figure 14-15. SIM Reset Status Register (SRSR)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
= Reserved
PIN
R
6
0
COP
R
5
0
ILOP
R
4
0
ILAD
R
3
0
MENRST
R
2
0
LVI
R
1
0
Freescale Semiconductor
Bit 0
R
0
0