MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 212

• Manufacturer Part Number: MC908MR32CFUE
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR32CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 6
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Peripheral Interface Module (SPI)
SPE — SPI Enable Bit
SPTIE— SPI Transmit Interrupt Enable Bit
15.12.2 SPI Status and Control Register
The SPI status and control register (SPSCR) contains flags to signal these conditions:
The SPI status and control register also contains bits that perform these functions:
SPRF — SPI Receiver Full Bit
ERRIE — Error Interrupt Enable Bit
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This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. See
Resetting the
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
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This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt (DMAS = 0), the CPU clears SPRF by reading the SPI status and
control register with SPRF set and then reading the SPI data register.
Reset clears the SPRF bit.
This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears
the ERRIE bit.
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
1 = Receive data register full
0 = Receive data register not full
1 = MODF and OVRF can generate CPU interrupt requests.
0 = MODF and OVRF cannot generate CPU interrupt requests.
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Address: $0045
Reset:
Read:
Write:
SPI. Reset clears the SPE bit.
Figure 15-15. SPI Status and Control Register (SPSCR)
SPRF
Bit 7
R
R
0
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
= Reserved
ERRIE
6
0
OVRF
R
5
0
MODF
R
4
0
SPTE
R
3
1
MODFEN
2
0
SPR1
1
0
Freescale Semiconductor
SPR0
Bit 0
0
15.8