MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 35

• Manufacturer Part Number: MC908MR32CFUE
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR32CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 6
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
U = Unaffected
$FE0C
$FE0D
$FE0E
$FE00
$FE01
$FE03
$FE08
$FE0F
$FF7E
$FFFF
Addr.
LVI Status and Control Register
FLASH Block Protect Register
Break Address Register High
Break Address Register Low
SIM Break Status Register
SIM Reset Status Register
Break Status and Control
X = Indeterminate
Register Name
FLASH Control Register
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 8 of 8)
SIM Break Flag Control
COP Control Register
Register (BRKSCR)
Register (SBFCR)
See page 191.
See page 192.
See page 193.
See page 254.
See page 254.
See page 254.
See page 38.
See page 99.
See page 43.
See page 77.
(COPCTL)
(LVISCR)
(FLBPR)
(SBSR)
(SRSR)
(BRKH)
(FLCR)
(BRKL)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read: LVIOUT
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
BCFE
BRKE
BPR7
Bit 15
Bit 7
POR
Bit 7
R
R
R
R
1
0
0
0
0
0
0
0
0
= Reserved
BRKA
BPR6
PIN
14
R
R
R
R
6
0
0
0
0
6
0
0
0
0
0
TRPSEL
BPR5
COP
13
R
R
R
5
0
0
0
0
5
0
0
0
0
0
Low byte of reset vector
BPR4
ILOP
Bold
Unaffected by reset
Clear COP counter
12
R
R
R
R
4
0
0
0
0
4
0
0
0
0
0
0
= Buffered
HVEN
BPR3
ILAD
11
R
R
R
R
3
0
0
0
3
0
0
0
0
0
0
MENRST
MASS
BPR2
10
R
R
R
R
2
0
0
0
2
0
0
0
0
0
0
= Unimplemented
ERASE
BPR1
BW
LVI
R
R
R
1
0
0
0
9
0
1
0
0
0
0
0
0
Memory Map
BPR0
PGM
Bit 0
Bit 8
Bit 0
R
R
R
R
0
0
0
0
0
0
0
0
0
0
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