R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 328

MCU 256KB FLASH 64K 144-LQFP

R4F24269NVFQV

Manufacturer Part Number
R4F24269NVFQV
Description
MCU 256KB FLASH 64K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24269NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
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Part Number:
R4F24269NVFQV
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Section 6 Bus Controller (BSC)
(b) Normal space access after a continuous synchronous DRAM space write access
If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is
not in accordance with the DRMI bit in DRACCR.
Figure 6.92 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
Page 298 of 1372
Figure 6.92 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Precharge-sel
DQMU, DQML
Address bus
HWR, LWR
Data bus
CKE
CAS
RAS
WE
RD
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
φ
PALL ACTV
Column
address
T
Continuous synchronous
DRAM space write
p
address
address
Row
Row
T
r
NOP WRIT
T
c1
address
Column
T
c2
Idle cycle
External address space read
T
i
External address
External address
T
1
High
NOP
T
2
H8S/2426, H8S/2426R, H8S/2424 Group
T
3
READ
Synchronous
DRAM space read
T
Column address 2
REJ09B0466-0350 Rev. 3.50
c1
T
Cl
NOP
T
c2
Jul 09, 2010

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