R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 499

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
(4)
DMA transfer is aborted when an NMI interrupt is generated. The EDA bit is cleared to 0 in all
channels. In external request mode, DMA transfer is performed for all transfer requests for which
EDRAK has been output. In dual address mode, processing is executed for the write cycle
following the read cycle.
In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the
transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the
block transfer was not carried out normally.
When transfer is aborted, register values are retained, and as the address registers indicate the next
transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit
is 1 in EDMDR, transfer can be resumed from midway through a block.
(5)
The EXDMAC is initialized in hardware standby mode and by a reset. EXDMA transfer is not
guaranteed in these cases.
8.4.13
The read and write operations in an EXDMA transfer cycle are indivisible, and a refresh cycle*,
external bus release cycle, or internal bus master (CPU, DTC, or DMAC) external space access
cycle never occurs between the two.
When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh*
or external bus release state may be inserted after the write cycle. As the internal bus masters are
of lower priority than the EXDMAC, external space accesses by internal bus masters are not
executed until the EXDMAC releases the bus.
The EXDMAC releases the bus in the following cases:
1. When EXDMA transfer is performed in cycle steal mode
2. When switching to a different channel
3. When transfer ends in burst transfer mode
4. When transfer of one block ends in block transfer mode
5. When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1
Note: * Not supported in the 5-V version.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
(however, the bus is not released between read and write cycles)
Transfer Abort by NMI Interrupt
Hardware Standby Mode and Reset Input
Relationship between EXDMAC and Other Bus Masters
Section 8 EXDMA Controller (EXDMAC)
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